1. Field of the Invention
This invention relates to integrated circuit fabrication, and more particularly, to an integrated circuit in which gate structures for n-channel and p-channel transistors are separately optimized, and to a method for producing this integrated circuit.
2. Description of the Relevant Art
Metal-oxide-semiconductor field effect transistors (MOSFETs) are a fundamental building block of most modem integrated circuits. Fabrication of a MOSFET involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide ("oxide"), is formed on a portion of semiconductor substrate which is doped with either n-type or p-type impurities. A gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. The channel of the transistor is located under the gate dielectric, between the source and drain.
Two basic types of MOSFET may be formed: n-channel MOSFETs or p-channel MOSFETs. In an n-channel MOSFET, the portion of the substrate which forms the channel is doped p-type, and the source and drain regions are doped n-type. In a p-channel MOSFET, on the other hand, the reverse is true: p-type source and drain regions are formed in an n-type region of the substrate. Integrated circuits may be made using exclusively n-channel transistors (NMOS technology) or exclusively p-channel transistors (PMOS tcchnology). However, several advantages may be associated with combining n-channel and p-channel transistors within a circuit. Complementary MOS (CMOS) technology, in which each logic gate in the circuit contains both an n-channel and a p-channel transistor, is very widely used in current integrated circuit manufacture. A major advantage of CMOS technology is that power consumption of the resulting circuitry is reduced by comparison to NMOS or PMOS technology. CMOS thereby allows a higher density of transistors to be used in an integrated circuit without incurring power dissipation and circuit heating problems.
The high transistor density which may be used makes CMOS technology particularly suitable in light of the trend in modern integrated circuit manufacture toward production of transistors having feature sizes as small as possible. Many modern day processes employ features, such as gate conductors and interconnects, which have less than 0.3 .mu.m critical dimension. As feature size decreases, the sizes of the resulting transistors and the interconnect between transistors also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
CMOS circuits are typically formed by establishing both n-type and p-type active regions within a semiconductor substrate. The active regions may be separated by isolation regions formed within the substrate. A gate dielectric layer and a gate conductor layer, typically polysilicon, are typically formed over all of the active regions simultaneously. These layers are then patterned to form a gate structure, including a gate dielectric and gate conductor, over each active region. Fabrication of the gate structures before formation of the source and drain regions of the transistors is important to the realization of "self-aligned" transistor structures. The source and drain regions formed in self-aligned structures exhibit minimal overlap with the transistor gate, minimizing the parasitic capacitances that limit high-frequency transistor performance. In general, the self-alignment is achieved by fabricating a gate conductor, and subsequently using the gate conductor as a mask for implantation of dopant impurities to form the source and drain. Because it is formed before the implantation and subsequent annealing of the source and drain impurities, the gate conductor is made from a material which can withstand high-temperature processing.
Much of the transistor fabrication occurring subsequent to the gate structure formation is done separately for n-channel and p-channel transistors. Photoresist masking of, for example, the p-type active regions may be done during formation of source and drain regions for the p-channel transistors fabricated on the n-type active regions. Similarly, source and drain regions for the n-channel transistors may be formed while the n-type active regions are protected by photoresist. Other attributes which may be different for n-channel and p-channel transistors in a circuit include the doping of the polysilicon gate conductor. While in some fabrication processes gate conductors for both n-channel and p-channel devices are made from n-type polysilicon, some processes use n-type polysilicon gate conductors for n-channel transistors, and p-type polysilicon gate conductors for p-channel transistors.
Although some aspects of CMOS fabrication are different for n-channel and p-channel transistors, as noted above, one attribute which is typically the same for both the n-channel and p-channel transistors is the basic composition of the gate structure. "Composition of the gate structure" is used herein to refer to both the materials used to form the gate structure and the layer thicknesses of those materials. For example, in a conventional CMOS circuit, gate dielectrics are typically formed from oxide for both n-channel and p-channel transistors, while gate conductors are formed from polysilicon (the polysilicon gate conductors may have opposite doping types, as described above). Furthermore, since gate structures for both the n-channel and p-channel transistors are generally patterned from a common dielectric/polysilicon stack, the n-channel and p-channel gate structures typically have the same gate dielectric thicknesses and the same gate conductor thicknesses.
There are disadvantages to having the same composition of the n-channel and p-channel gate structures, however. In particular, problems may arise from the different dopants used to form the source/drain regions in n-channel and p-channel devices. The boron used to form source and drain regions in p-channel transistors is known to diffuse significantly faster than the n-type dopants, such as arsenic and phosphorus, typically used in n-channel transistors. This rapid boron diffusion can have various consequences for p-channel transistors. For example, diffusion of source and drain impurities into the channel can shorten the effective length of the channel. The gate lengths, or nominal channel lengths, of p-channel transistors can therefore not be reduced to the extent that they can for n-channel transistors. Boron may also diffuse across the gate dielectric in a p-channel transistor, either from the polysilicon gate conductor into the channel (when p-type polysilicon is used for the gate), and/or from source/drain portions underlying the gate conductor (due to lateral diffusion) up into the polysilicon gate conductor. In either case, such diffusion across the gate dielectric can alter the threshold voltage of the transistor, by changing the work function of the polysilicon gate and/or by changing the channel doping. The gate dielectrics of p-channel transistors should therefore not be made too thin, and diffusion barrier layers associated with either the gate dielectric or the gate conductor may be desirable.
The limitations described above for p-channel transistors are generally much less relevant to n-channel transistors, and in fact pose a problem for getting optimum performance from n-channel transistors. To the extent possible, it is desirable to reduce transistor feature sizes, as discussed above. It would therefore be desirable to reduce the gate length of the n-channel transistors, which do not employ boron-doped source and drain regions. The feature size reduction discussed above necessitates a reduction of overall transistor dimensions and operating voltages known as "scaling". As gate lengths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. These device dimensions and voltages are not necessarily each decreased by the same factor. One dimension which is generally decreased when gate lengths are decreased, however, is gate dielectric thickness. Gate dielectric thickness for n-channel transistors should therefore be reduced if n-channel transistors having reduced gate length are to be fabricated.
An optimized n-channel transistor structure having a shortened gate length and thinner gate dielectric as discussed above is in conflict with the requirements of an optimized p-channel transistor having a thicker gate oxide and possibly a diffusion barrier in the gate structure, because the gate structure composition is the same for n-channel and p-channel transistors in a conventional circuit. It would therefore be desirable to develop a method for forming separate gate structures for n-channel and p-channel transistors. The method should allow self-aligned n-channel and p-channel transistors to be fabricated.